1. Field of the Invention
The present invention relates to a digitally controlled oscillator, and more particularly to a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates.
2. Description of the Background Art
An advance in semiconductor processing technology and an increasing number of systems which require a relatively small amount of power to operate encourage active research aimed at the substitution of an all digital phase locked loop for an analog phase locked loop. The all digital phase locked loop is required to widen its operation range, because the phase locked loop is used as a function block for supplying a clock signal to the system.
Generally, a digitally controlled oscillator, built in the digital phase locked loop, determines the range in which the digital phase locked loop operates. The digitally controlled oscillator includes a delay stage including odd-number inverters which connect in series to each other. The digitally controlled oscillator generates an oscillation signal by feeding back a delay signal output from the delay stage into the delay stage. A phase and a frequency of the oscillation signal can be adjusted by adjusting a delay time in the delay stage, using a digital control signal.
FIG. 1 is a view of an embodiment of a conventional digitally controlled oscillator.
Referring to FIG. 1. the digitally controlled oscillator 100 includes odd-number delay stages 110 through 130. Each of the delay stages 110 through 130 has tri-state inverters which connect in parallel to each other. The delay time in each of the delay stages is determined by adjusting the number of the tri-state inverters which operate among the tri-state inverters which connects in parallel to each other. An output from the third delay stage 130 is fed back into the first delay stage 110 to generate the oscillation signal.
FIG. 2 is a view of another embodiment of the conventional digitally controlled oscillator.
As shown in FIG. 2, the digitally controlled oscillator 200 includes coarse blocks 210 and 220 and a fine block 230.
The coarse blocks 210 and 220 includes the delay stage 210 and a multiplexer 220. The delay stage 210 includes a plurality of delay components 211 through 214. The multiplexer 220 selects one from among a plurality of delay signals, each having a different delay time, which are output from the delay stage 210, in response to an m (integer)-bit first control signal CON1. The fine block 230 reverses and delay a phase of the delay signal which is output from the multiplexer 220 in response to an n(integer)-bit second control signal CON2, and then feed back the phase-reversed and time-delayed delay signal into the delay stage 210.
Each of the delay components 211 through 214 generally includes a buffer which consists of two inverters connecting in series to each other. In this case, a minimum fluctuation unit of the delay time in the coarse blocks 210 and 220 is twice the delay time in the buffer, i.e., the delay time in the inverter.
In the fine block 230, the delay time is finely adjusted by changing a configuration of a circuit in response to the n-bit second control signal CON2. The adjustable delay time in the fine block 230 should be larger than, or equal to the minimum fluctuation unit of the delay time in the coarse blocks 210 and 220. Therefore, the adjustable delay time in the fine block 230 is more than two times, or equal to the delay time in the buffer, i.e. the delay time in the inverter.
FIG. 3 is a view of another embodiment of the conventional digitally controlled oscillator.
As shown in FIG. 3, the digitally controlled oscillator 300 includes a digital-to-analog converter 310 and a voltage controlled oscillator 320. The digitally controlled oscillator 300 uses the analog-type voltage controlled oscillator 320.
The three types of the conventional digitally controlled oscillator shown in FIGS. 1 through 3, when their operation range is widened, generally tend to operates at a low frequency.
In the digitally controlled oscillator 100 shown in FIG. 1, when the number of the tri-state inverters connecting in parallel to each other, making up the delay stage, is increased to widen its operation range, load capacitance of each delay stage is also increased. Thus, the maximum frequency at which the digitally controlled oscillator 100 decreases. In the digitally controlled oscillator 200 shown in FIG. 2, when the number of delay stage 210 making up the coarse block 210 and 220 is increased to widen its operation range, a fan-in value of the multiplexer 220 increases. Thus, the delay time in the multiplexer 220 increases. In the digitally controlled oscillator 300 shown in FIG. 3, when the operation range of the voltage controlled oscillator is increased to widen its operation range, the frequency at which the digitally controlled oscillator 300 decreases due to characteristics of the circuit.